1664706005 This Intel Silicon Photonics Connector is a HUGE deal

This Intel Silicon Photonics Connector is a HUGE deal – ServeTheHome

Intel Silicon Photonics package on the desktopIntel Silicon Photonics package on the desktop

At Intel Innovation 2022 this week we saw what is perhaps the most interesting technology for servers, storage and networking equipment. It can redefine the entire space. Specifically, it is the new Intel Silicon Photonics Connector. Let’s dive into what Intel is doing with the new solution and why it’s such a big deal.

This Intel Silicon Photonics Connector is a HUGE deal

At the Intel Innovation 2022 Day 1 keynote, Pat Gelsinger called a Scottish Intel lab and we witnessed a great demo of a new technology. This is a new pluggable form factor for silicon photonics. One reason for this is that video and audio actually worked, even if this is not yet a matter of course in 2022. The real magic is that the Intel team showed a live demonstration of plugging in a new pluggable form factor for co-packaged optics.

Intel Silicon Photonics demo innovation 2022Intel Silicon Photonics demo innovation 2022

This pluggable optical module can be thought of as a smaller version of an MPO/MTP connector designed to connect directly to chip packages.

MPO MTP Male Female Face ViewMPO MTP Male Female Face View

Just to illustrate what this is connected to on your switch or NIC, the left 100GBASE-SR4 QSFP28 module on the left is the other end for this cable. You’ll notice that unlike the CWDM module (right), multiple dense fibers are connected along this MTP-12 link. For 100GBASE-SR4 there are four pairs, so eight of the 12 fibers are used, but these are the images we had on hand. In some of Intel’s animations, they actually start with an MTP-12 cable and then show it being plugged back into the new silicon photonic connector.

100GBASE SR4 and CWDM4 QSFP28100GBASE SR4 and CWDM4 QSFP28

This is delicate work. Here is an example of the painstaking lab work on this early unit.

Intel Silicon Photonics Innovation 2022Intel Silicon Photonics Innovation 2022

While many have seen pluggable network optics, the current world of silicon photonics has a very physical challenge. Intel knows how to make silicon photonics modules, but putting them on a chip is challenging because you have to connect fiber directly to the chip. Most current approaches involve “pigtails,” where short fiber runs run from the chip to a secondary connector.

Intel Silicon Photonics Package pigtail connectorsIntel Silicon Photonics Package pigtail connectors

We saw these braids recently. An example is the 4x 400G version we saw at Intel Vision 2022.

Intel Vision 2022 4x 400 Gbit/s silicon photonicsIntel Vision 2022 4x 400 Gbit/s silicon photonics

We also saw these pigtails in our co-packaged pre-pandemic Barefoot optic piece. Here are the packaged optical pigtails that look like the ones above connected to MPO/MTP connectors in yellow.

Intel Co packs Barefoot Tofino 2 and Silicon Photonics CoverIntel Co packs Barefoot Tofino 2 and Silicon Photonics Cover

To learn more about it, here is the video when STH YouTube had 10,000 subscribers before the pandemic. STH YouTube hit 100,000 a few hours ago.

If we delve a little into the demo we saw on stage, Intel has a photonic integrated circuit and an electronic integrated circuit together on the XPU package, and that’s what the electrical signaling on the package tells the handles photonics. Keeping the electrical signaling on a packet is much lower power than driving signals outside the packet. Given the demands on I/O performance, this is going to be a big deal in the future. Network switches already face this challenge given the amount of I/O they have. This will be one of the first segments in which chips will move to co-packaged optics. It will likely happen just a generation or two later than what we have shown in this 2020 article.

Intel Silicon Photonics Package with Pluggable Optics PIC and EICIntel Silicon Photonics Package with Pluggable Optics PIC and EIC

Intel’s innovation is something that looks like an AOC, or active optical cable, but appears to be more akin to a specialized multi-fiber connector like an MTP connector.

Intel Silicon Photonics Package CouplerIntel Silicon Photonics Package Coupler

If you take a close look at Intel’s test package, something else happens. We can see that one port is installed but there appears to be room for two more which have black covers in this photo.

Close Intel Silicon Photonics Package with Pluggable Optics DemoClose Intel Silicon Photonics Package with Pluggable Optics Demo

While this may seem far-fetched at first, consider that Intel’s own renderings depict a very similar three-port package. It looks like Intel will not only deliver co-packaged silicon photonics with a pluggable connector form factor, but is already working on multi-connector solutions with tons of bandwidth.

Intel Silicon Photonics Package with pluggable opticsIntel Silicon Photonics Package with pluggable optics

Of course, with multiple fibers, you don’t need dedicated fibers for storage, networking, compute, and storage, but the point is, that’s the vision. Intel can connect devices using optical network cables.

last words

The “so what” of it is really great. Read the tea leaves a bit, here were Raja Koduri’s notes (with Cool Ranch Doritos) from the piece Raja’s Chip Notes Lay Out Intel’s Path to Zettascale:

Raja Chip states the Intel HPC strategy 2022 2028Raja Chip states the Intel HPC strategy 2022 2028

You’ll see something called “Lightbender” or “Light Bender” as a codename and “SiPh” shorthand for silicon photonics in the 2024-2025 era along with Falcon Shores.

Intel’s strategy is to have a silicon photonics tile that can be packaged with other resources and chips can be expanded beyond current packaging technology by using optical interconnects. Imagine instead of being limited to 6-8 HBM cases due to packaging considerations, the HBM could sit outside the case and connect via optics, thereby allowing for larger HBM footprints.

We know chips will go into multiple tiles as we see from UCIe, so this will be a silicon photonics tile that must contain some form of EIC and PIC as shown in the Innovation 2022 demo.

Universal Chiplet Interconnect Express UCIe 1.0 coverageUniversal Chiplet Interconnect Express UCIe 1.0 coverage

What’s also exciting is that we can have fabric topologies in CXL 3.0. If you want to enable high-performance CXL communications on a larger rack scale, this would be a very useful technology.

CXL 3.0 Composable Systems exampleCXL 3.0 Composable Systems example

The innovation being shown at Innovation (yes, that just happened) 2022 isn’t that Intel can run silicon photonics. Hyper-scalers are already buying millions of silicon photonic modules in pluggable form factors from Intel. One of the biggest challenges for co-packaged optics and the introduction of silicon photonics into chips is the physical connection. The pigtail approach is often seen as a challenge to real-world service. Intel demonstrated its vision to go beyond optical pigtail bundles and move to a familiar pluggable connector-based approach. While we may not see the final mechanical design just yet, this is one of those small innovations that we expect to see some form factor standardized in this space over the next few years, and to help with adoption. Between UCIe, CXL and the next generation of network switches, this is an area that needs a common path forward. That’s what makes the Intel Silicon Photonics Connector a big deal.