1668132956 AMD EPYC Genoa wraps up Intel Xeon in stunning fashion

AMD EPYC Genoa wraps up Intel Xeon in stunning fashion – ServeTheHome

AMD EPYC 9654 Genoa CPU 1AMD EPYC 9654 Genoa CPU 1

The AMD EPYC 9004 series, codenamed Genoa, is nothing short of a game changer. We use that a lot in the industry, but that’s not a 15-25% improvement over the generations. The new AMD EPYC Genoa is changing the fundamentals of what it means to be a server. This is an improvement of 50-60% (or more) per socket, meaning we’re getting a 3:2 or 2:1 consolidation from a generation ago. If you move from 3-5 year old Xeon Scalable Servers (1st and 2nd generation) to EPYC, the consolidation potential is still immense, more like 4:1. There’s a lot more to this new series than just extra cores or a few new features. AMD EPYC Genoa is a game changer and we will detail why in this article.

This might be the longest piece about STH this year. We’re going to have a ton in here, and as I’m writing this a week before launch, we’ve had to trim the scope of this piece just to save time. That brings us to the point.

AMD EPYC 9004 Genoa: the video

This is a (very) long article. We also have a video, and this is perhaps one of the few pieces we do where it’s quicker to get a synopsis while looking at it than reading it. Here’s the video:

We’ve got a lot more detail in this article, but if you decide to podcast this later (you can even speed it up), feel free to check out a simple overview. As always, we recommend opening this video in its own window, tab, or app for a better viewing experience.

AMD EPYC Genoa Market Context: Today’s Market

AMD is launching the genoa part at a slightly strange timing. Intel still has its Ice Lake and Cooper Lake generation Xeon parts as part of its 3rd Gen Intel Xeon Scalable family. That means Intel has chips with up to 28 cores and 6 DDR4 channels that can be scaled to 4-8 sockets (and up to one) and 40 cores and 8 DDR4 channels for 2 socket applications. The full instruction set is mostly common, but some examples, like bfloat16 support, are not identical between the two.

AMD EPYC 9004 Genoa with Milan Rome Intel Xeon Ice Lake Sapphire Rapids Core Ampere Altra Max 2 13th GenAMD EPYC 9004 Genoa with Milan Rome Intel Xeon Ice Lake Sapphire Rapids Core Ampere Altra Max 2 13th Gen

If you take a top-end dual-socket Ice Lake server with 2x 40-core Ice Lake Xeon CPUs and a top-end 4-socket server with 4x 28-core CPUs, you get They have a total of 192 cores or the same as a top-end dual-socket Genoa server. Aggregated storage bandwidth would also be in a similar range. In this review, Genoa might feel like an asymmetric advancement, and that’s because it is. Intel will have its answer in two months, but it won’t compete directly with the 84- and 96-core Genoa on a core-by-core basis. Intel will instead focus on the 16-64 core mainstream market when Sapphire Rapids comes out in 2023.

AMD EPYC 9554 EPYC 9654 and EPYC 7374F Genoa 2AMD EPYC 9554 EPYC 9654 and EPYC 7374F Genoa 2

The chips themselves are absolutely gargantuan, as are the resources they offer. Here is the lscpu output of a dual AMD EPYC 9654 96-core processor system with 192 cores, 384 threads and 768MB combined L3 cache.

AMD EPYC 9654 2P Lscpu outputAMD EPYC 9654 2P Lscpu output

Our technical readers in the screenshot above will also note that there are a large number of new instructions including AVX-512 and AI-focused instructions including VNNI from Ice Lake Xeons through to Cooper Lake Xeons’ bfloat16 support.

AMD EPYC 9654 Genoa in SP5 Socket 1AMD EPYC 9654 Genoa in SP5 Socket 1

AMD’s approach is simple. It uses the same basic Zen4 CCD chip that it uses in its Ryzen 7000 series desktop products and combines more of it in one package along with a much larger and more powerful I/O chip. What is new for this generation is that AMD uses up to 12 instead of up to 8 of these CCDs as in the EPYC 7002 (Rome) and EPYC 7003 Milan generations.

2p AMD EPYC 9654 QCT development system topology2p AMD EPYC 9654 QCT development system topology

Knowing that AMD will have a roughly 50% core count advantage at the top end, Intel is focused on fighting at the heart of the market buying lower core count SKUs and using accelerators to deliver performance gains that can offer far beyond the pure cores.

Intel Sapphire Rapids Intel Innovation 2022 Acceleration Unboxing 21Intel Sapphire Rapids Intel Innovation 2022 Acceleration Unboxing 21

AMD EPYC 9004 CPUs are the beginning of a very different environment in the server world. While relatively large, they won’t be AMD’s most powerful on a per-core basis this cycle, nor even AMD’s highest core count. Genoa is simply AMD’s mainstream part.

AMD EPYC Genoa Market Context: There’s More!

Perhaps the biggest difference between this launch and some of the previous launches is positioning. AMD now has enough scale to go beyond a single design for the entire market and scale cores, frequency and TDP. Instead, AMD will now have segment-specific solutions for some of its larger segments.

AMD EPYC 9554 EPYC 9654 and EPYC 7374F Genoa 1AMD EPYC 9554 EPYC 9654 and EPYC 7374F Genoa 1

The first of these solutions is the new AMD EPYC Bergamo. It uses the same AMD Socket SP5 as Genoa, but with an emphasis on maximizing core count for cloud workloads. AMD will reduce cache sizes to accommodate more cores, but otherwise this will be AMD’s high core count solution with up to 128 cores per socket. The Genoa headline reads only 96 cores. We’ll be happy about a generational 50% increase in core count throughout this article, but Bergamo is another 33% increase from the 96-core mark and is slated for H1 2023. This is AMD’s answer to the threat of arm server CPUs.

AMD FAD 2022 EPYC Roadmap BergamoAMD FAD 2022 EPYC Roadmap Bergamo

Genoa-X will break the 1GB/socket L3 cache limit. With standard genoa we get up to 384MB L3 cache per socket or 768MB L3 cache per 2P server. With Milan-X we had 64 cores and up to 768 MB of L3 cache per socket. We expect AMD to offer over 2GB of L3 cache in a dual-socket server in 2023. Genoa-X will target applications such as B. in the HPC area, where the addition of 3D V-Cache increases the data locality to the point that less energy is wasted when moving data. Genoa-X is for HPC and we hope other industries will be served with parts like frequency-optimized high-cache parts for databases, but AMD hasn’t talked about it yet.

AMD FAD 2022 EPYC Roadmap Genoa X and SienaAMD FAD 2022 EPYC Roadmap Genoa X and Siena

The new SP5 socket servers are so large that they are simply too big for many applications.

AMD EPYC 9654 Genoa in SP5 Socket 3AMD EPYC 9654 Genoa in SP5 Socket 3

The new AMD EPYC Siena platform will be designed to power more edge devices. It’s a hot field, and we’ve already seen companies like Ampere, with its ARM-based processors, begin to show proof-of-concept for the intelligent edge.

AMD FAD 2022 AMD Instinct MI300 DC APUAMD FAD 2022 AMD Instinct MI300 DC APU

AMD Instinct MI300 is maybe the other HPC part. This combines x86 and GPU IP into packages that also have high-speed memory onboard. NVIDIA will have Grace Arm CPU and NVIDIA GPU modules and Intel with Falcon Shores XPUs. This is an industry trend that we expect to see in supercomputers and HPC.

The bottom line is that today’s AMD EPYC Genoa launch differs from previous launches in Naples, Rome and Milan. Genoa is not expected to serve the entire market with HPC, cloud and edge markets with various AMD chips later in 2023.

So let’s move on to making Genoa.